Dies or wafers, and the like, may be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes. This can include stacking one or more dies or wafers on a larger base die or wafer, stacking multiple dies or wafers in a vertical arrangement, and various combinations of these. Dies may be stacked on wafers or wafers may be stacked on other wafers prior to singulation. The dies or wafers may be bonded in a stacked arrangement using various bonding techniques, including using direct dielectric bonding, non-adhesive techniques, such as a ZiBond® direct bonding technique or a hybrid bonding technique, such as DBI®, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), a subsidiary of Xperi Corp. (see for example, U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety).
When bonding stacked dies or wafers using a direct bonding technique, it is desirable that the surfaces of the dies or wafers to be bonded be extremely flat and smooth. For instance, the surfaces should have a very low variance in surface topology, such that the surfaces can be closely mated to form a lasting bond. It is also desirable that the surfaces be clean and free from impurities, particles, and/or other residue. The presence of undesirable particles for instance, can cause the bond to be defective or unreliable at the location of the particles. For instance, some particles and residues remaining on bonding surfaces can result in voids at the bonding interfaces between the stacked dies.
Respective mating surfaces of the bonded dies or wafers often include embedded conductive interconnect structures, arranged so that the conductive interconnect structures from the respective surfaces are joined during the bonding. The joined interconnect structures form continuous conductive interconnects (for signals, power, etc.) between the stacked dies. Other embedded metallic structures (or pads) may be used for probing/testing/programming a circuit or device of the die during manufacturing and prior to bonding. These probe pads may not have corresponding metallic structures for bonding or may not have further use after bonding.
Generally at least some of the metallic interconnects or pads are probed prior to bonding. In many cases, the softer metallic pads may be deformed by the probe's contact with the pads, displacing some pad material and creating a notable variance in the die's overall surface topology. The variance may be enough to weaken a direct bond or reduce the reliability of the bond at the location of the surface variance. For example, a variance defect may be 0.5 to 1 micron in height, or greater.
It may be desirable to attempt to smooth the variances in the surface topology of the dies (e.g., smooth the displaced pad material or “probe mark”) to ensure a more reliable bond. However, in most cases, foundries are less willing to bring dies that have been outside of extreme clean room environments back into those environments for further processing. Also, touch-up chemical-mechanical polishing (CMP) of the damaged die surfaces adds an additional processing step, increasing the manufacturing cost of the dies.